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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sounddriver is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal aud_adcdat : IN STD_LOGIC;
                 signal chipselect : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal read : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal write : IN STD_LOGIC;
                 signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

              -- outputs:
                 signal aud_adclrck : OUT STD_LOGIC;
                 signal aud_bclk : INOUT STD_LOGIC;
                 signal aud_dacdat : OUT STD_LOGIC;
                 signal aud_daclrck : OUT STD_LOGIC;
                 signal aud_xck : OUT STD_LOGIC;
                 signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity sounddriver;


architecture europa of sounddriver is
component soundcontroller is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal aud_adcdat : IN STD_LOGIC;
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

                 -- outputs:
                    signal aud_adclrck : OUT STD_LOGIC;
                    signal aud_bclk : INOUT STD_LOGIC;
                    signal aud_dacdat : OUT STD_LOGIC;
                    signal aud_daclrck : OUT STD_LOGIC;
                    signal aud_xck : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component soundcontroller;

                signal internal_aud_adclrck :  STD_LOGIC;
                signal internal_aud_dacdat :  STD_LOGIC;
                signal internal_aud_daclrck :  STD_LOGIC;
                signal internal_aud_xck :  STD_LOGIC;
                signal internal_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --the_soundcontroller, which is an e_instance
  the_soundcontroller : soundcontroller
    port map(
      aud_adclrck => internal_aud_adclrck,
      aud_bclk => aud_bclk,
      aud_dacdat => internal_aud_dacdat,
      aud_daclrck => internal_aud_daclrck,
      aud_xck => internal_aud_xck,
      readdata => internal_readdata,
      address => address,
      aud_adcdat => aud_adcdat,
      chipselect => chipselect,
      clk => clk,
      read => read,
      reset_n => reset_n,
      write => write,
      writedata => writedata
    );


  --vhdl renameroo for output signals
  aud_adclrck <= internal_aud_adclrck;
  --vhdl renameroo for output signals
  aud_dacdat <= internal_aud_dacdat;
  --vhdl renameroo for output signals
  aud_daclrck <= internal_aud_daclrck;
  --vhdl renameroo for output signals
  aud_xck <= internal_aud_xck;
  --vhdl renameroo for output signals
  readdata <= internal_readdata;

end europa;

